The present application contains subject matter related to the subject matter disclosed in U.S. patent application Ser. No. 09/641,374 entitled xe2x80x9cVideo, Audio and Graphics Decode, Composite and Display System,xe2x80x9d U.S. patent application Ser. No. 09/643,223 entitled xe2x80x9cVideo and Graphics System with MPEG Specific Data Transfer Commands,xe2x80x9d U.S. patent application Ser. No. 09/640,870 entitled xe2x80x9cVideo and Graphics System with Video Scaling,xe2x80x9d U.S. patent application Ser. No. 09/640,869, now issued as U.S. Pat. No. 6,538,656 on Mar. 25, 2003 entitled xe2x80x9cVideo and Graphics System with a Data Transport Processor,xe2x80x9d U.S. patent application Ser. No. 09/641,930 entitled xe2x80x9cVideo and Graphics System with a Video Transport Processor,xe2x80x9d U.S. patent application Ser. No. 09/641,935, now issued as U.S. Pat. No. 6,573,905 on Jun. 3, 2003 entitled xe2x80x9cVideo and Graphics System with Parallel Processing of Graphics Windows,xe2x80x9d U.S. patent application Ser. No. 09/642,510 entitled xe2x80x9cVideo and Graphics System with a Single-Port RAM,xe2x80x9d and U.S. patent application Ser. No. 09/642,458 entitled xe2x80x9cVideo and Graphics System with an Integrated System Bridge Controller,xe2x80x9d all filed Aug. 18, 2000.
The present invention relates generally to integrated circuits, and more particularly to an integrated circuit system for processing and displaying video and graphics.
Video and graphics systems are typically used in television control electronics, such as set top boxes, integrated digital TVs, and home network computers. Video and graphics systems typically include a display engine that may perform display functions. Video and graphics systems may include a video decoder for decoding compressed video data such as MPEG video data. The compressed video data typically are decoded serially, making it difficult sometimes to decode the compressed video data within the allotted number of clock cycles.
This application includes references to both graphics and video, which reflects in certain ways the structure of the hardware itself. This split does not, however, imply the existence of any fundamental difference between graphics and video, and in fact much of the functionality is common to both. Graphics as used herein may include graphics, text and video.
In one embodiment of the present invention, a video decoding system having one or more row decoding engines decodes video data, which is organized into a number of groups. One or more row decoding engines concurrently decode two or more groups of video data. The row decoding engines may be integrated on an integrated circuit chip. Each row decoding engine may concurrently decode at least two groups of video data. The row decoding engines may have a pipelined architecture for concurrently decoding multiple groups of video data.
Another embodiment of the present invention is a method of decoding video data. A video decoder receives multiple groups of video data and concurrently decodes two or more groups of video data. The video data may include MPEG-2 video data organized into SLICEs. When concurrently decoding two or more groups of video data, the video decoder may decode a first portion of a first macroblock while concurrently decoding a second portion of a second macroblock.
Yet another embodiment of the present invention is a video and graphics system having a transport processor for receiving one or more compressed data streams and for extracting video data, a video decoder including one or more row decoding engines for decoding the video data to generate decoded video data, and a video compositor for blending the decoded video data with graphics. The video data is organized into rows, and the one or more row decoding engines concurrently decode two or more rows of video data. The video and graphics system may be implemented on an integrated circuit chip. The video data may include SDTV video data as well as HDTV video data.